Implementation of energy-efficient low-power CMOS 4:2 compressor using DG FinFET technique

The Double-Gate FinFET technique is proposed in this work for the implementation of a CMOS 4:2 compressor. The main objective of this study is to reduce leakage power and leakage current while maintaining comparable performance with fewer transistors. This paper presents a high-performance CMOS 4:2 compressor based on an optimized logic architecture. The proposed Double-Gate FinFET approach reduces process variation effects in CMOS 4:2 compressor circuits, mainly by decreasing leakage power and delay. Double-Gate FinFET technology is suitable for logic cells because it provides improved speed, lower threshold-voltage operation, reduced leakage, and enhanced performance. The proposed CMOS 4:2 compressor design was simulated using Cadence Virtuoso at 90 nm technology.